In pipelined microprocessor architectures, such as a complex instruction-set computing (CISC) architecture, instructions may vary in length. Furthermore, instructions may be stored in an unaligned manner before being decoded and executed. Therefore, the length of the instructions may first need to be determined in order to properly align the instructions for execution.
FIG. 1 illustrates a typical instruction format of an instruction, such as one associated with an Intel® x86 processor architecture of Intel Corporation of Santa Clara, Calif. The instruction illustrated in FIG. 1 includes a prefix 101, an opcode 105, a MOD/RM field 110, a SIB field 115, a displacement field 120, and an immediate field 125.
The prefix appears before the opcode and may override various default attributes associated with the opcode. For example, a prefix may override the default size of the operand, the default size of the address specifier, and/or the default segment. Furthermore, the prefix may indicate a string instruction loop and/or indicate a bus lock cycle while executing an instruction. Prefixes that effect the length decoding of instruction include the overriding address size prefix, the overriding operand size prefix, and the repeat prefix.
The operand size override prefix may alter the default size of an operand associated with an instruction. For example, a 16-bit instruction containing the operand size override prefix may contain a 32-bit operand instead of the default 16-bit operand. Conversely, a 32-bit instruction containing the operand size override prefix may contain a 16-bit operand instead of the default 32-bit operand.
The address size override prefix may alter the default size of the address associated with the instruction. For example, a 16-bit instruction containing the address size override prefix may contain a 32-bit address instead of the default 16-bit address. Conversely, a 32-bit instruction containing the address size override prefix may contain a 16-bit address instead of the default 32-bit address.
The opcode identifies the operation to be performed by the instruction. Furthermore, the opcode may specify the number of immediate bytes, presence of the MOD/RM field, and/or displacement bytes. For example, an opcode may specify up to 6 displacement bytes or up to 4 immediate bytes.
The MOD/RM byte indicates the type of source and/or destination operands that are to be used in conjunction with an instruction. For example, the MOD/RM byte may indicate the existence within the instruction of up to four displacement bytes or a scale index (SIB) byte.
The SIB byte indicates other complex addressing modes. For example, the SIB byte may specify up to four displacement bytes.
Because each instruction may vary in length according to the above fields, it is necessary first determine the length of the instruction before it can be decoded and subsequently executed by a processor. Typical instruction length decoders are able to length decode only one instruction per processor clock cycle.